This invention relates generally to electronic memories of a type formed on integrated circuits with memory cells having electrically floating gates, and, more specifically, to an arrangement of such cells and the erasure of a block of cells at a time.
Flash electrically erasable and programmable read only memories (EEPROMs) have an advantage of providing a large amount of non-volatile data storage in a small package. Usually, such a memory includes an array of EEPROM cells in rows and columns, along with addressing decoders, sense amplifiers and other peripheral circuits necessary to operate the array. In addition to the charge on a floating gate affecting the conduction between source and drain regions of the individual memory cells, a control gate which extends across a row of such cells to form a memory word line also controls the floating gate potential through a capacitive coupling with the floating gate. The source and drain regions form the memory array bit lines. The state of each memory cell is altered by controlling the amount of electron charge on its floating gate. One or more cells are usually programmed at one time by applying proper voltages to their control gates, sources and drains to cause electrons to be injected onto the floating gates. Prior to such programming, a block (sector) of such cells is generally erased to a base level by removing electrons from their floating gates to an erase electrode. In one form of device, this erase electrode is the source region of the cells. In another form of the device, a separate erase gate is provided.
The storage density of flash EEPROM memories is being increased. As is occurring with integrated circuits generally, the sizes of individual circuit elements are being shrunk as processing technology improves. In addition, flash EEPROM memory cells can be operated to store more than one bit of data by establishing multiple charge storing states for each cell. The effect of these trends is to shrink the size of the memory blocks (sectors) which store a set amount of data.
The erase electrodes of the memory cells in a block (sector) are arranged so that all the cells in the block (sector) are erased at one time. In the memory architecture of SunDisk Corporation, each sector contains 512 bytes of user data plus some overhead including a header for the sector data. Other architectures have much larger sector sizes, 64k bytes being one of the larger. In either case, if the block (sector) size is kept constant, then increasing memory capacity results in a larger proportion of the circuit chip area having to be devoted to interconnection lines and peripheral circuits to control the increasing number of blocks (sectors) that are being formed.
Therefore, it is a principal object of the present invention to reduce the extent of interconnection lines and peripheral circuits necessary to support a flash EEPROM array whose storage capacity is being increased.
During erasure of an EEPROM cell, electrons are pulled from the cell's floating gate, as a result of the Fowler-Nordheim tunneling mechanism, by an electrical field created between the floating gate and the erase electrode. The voltage applied to the erase electrode for erasure depends upon the approach used to erase the EEPROM cell. This voltage is in a range of about 9-13 volts when erasure is through a thin silicon dioxide layer, such as occurs when the erase electrode is the source diffusion, and about 15-23 volts when erasure is through an oxide layer interposed between a polysilicon floating gate and a polysilicon erase gate. For moderate values of erase currents, it is typical to generate an erase voltage of 10 volts or higher on the memory chip from a single voltage supply to the chip of 3 or 5 volts. This eliminates the need for the user to provide two different power supply voltages to the circuit chip. However, for a high erase voltage of about 20 volts or more, the circuit requires a significant amount of area and increases the complexity of the processing necessary to form the circuit. Also, the yield from the manufacturing process and the reliability of the resulting circuit decrease as the magnitude of the internally generated voltage increases.
Therefore, it is another principal object of the present invention to provide a technique for minimizing the magnitude of the erase voltage which must be generated on memory chip.